SK Hynix has announced it has finished development of its 128-layer 1 terabit 3D TLC NAND flash. The new memory features the company’s charge trap flash (CTF) design, along with the peripheral under cells (PUC) architecture that the company calls ‘4D’ NAND, announced some time ago. The new 128-layer TLC NAND flash devices will ship to interested parties in the second half of this year, and SK Hynix intends to offer products based on the new chips in 2020. SK Hynix’s 1 Tb 128-layer TLC NAND chip features four planes as well as a 1400 MT/s interface at 1.2 Volts. The quad-plane architecture along with a 1400 MT/s I/O bus will make the new TLC NAND devices not only significantly denser (in terms of Gb per mm2) than previous-generation products, but also at least 16% faster. In fact, real-world performance increase could be even higher as SK Hynix once said that its CTF design would enable a faster program time (tPROG) as well as a faster read time (tR). To stack 128 layers inside its 6th Generation 3D NAND chips, the company had to use a multi-stacked design along with numerous new technologies, including ultra-homogeneous vertical etching technology as well as high-reliability mul...